1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, more particularly an array substrate for a liquid crystal display (LCD) device and a fabricating method thereof.
2. Discussion of the Related Art
LCD devices have been developed as next generation display devices because of their lightweight, thin profile, and low power consumption. In general, an LCD device is a non-emissive display device that displays images using optical anisotropic properties of a liquid crystal material that is interposed between a thin film transistor (TFT) array substrate and a color filter (C/F) substrate. Presently, among the various types of LCD devices commonly used, active matrix LCD (AM-LCD) devices have a high resolution and are superior in displaying moving images.
The AM-LCD device includes a thin film transistor (TFT) at each pixel region as a switching device, a first electrode for ON/OFF, and a second electrode used for a common electrode. The operational properties of LCD devices depends on the resistance of the electrodes connecting the TFT and on the resistance of the lines applying signals to the electrode. Therefore, a material selection of the electrodes and lines is very important.
FIG. 1 is a schematic plan view showing an array substrate for a liquid crystal display device according to the related art. As shown in FIG. 1, thin film transistors (TFTs) T in matrix are formed on a substrate 10, referred to as an array substrate. The TFTs T act as switching devices. Each TFT T includes a gate electrode 14, an active layer 20 over the gate electrode 14, and source and drain electrodes 24 and 26. Moreover, each TFT T is connected to a gate line 12 and a data line 28.
A pixel region P is defined by the gate line 12 and the data line 28. A pixel electrode 34 is formed in the pixel region P and is connected to the thin film transistor T. The gate electrode 14 extends from the gate line 12, the source electrode 24 extends from the data line 28, and the drain electrode 26 is spaced apart from the source electrode 24. A gate pad 16 is formed at one end of the gate line 12 and a data pad 30 is formed at one end of the data line 28. The gate pad 16 is wider than the gate line 12 and the data pad 30 is wider than the data line 28. A gate pad terminal 36 and a data pad terminal 38 are formed over the substrate 10 and are connected to the gate pad 16 and data pad 30, respectively. The gate and data pad terminals 36 and 38 are formed of transparent conductive materials, such as indium tin zinc oxide (ITZO).
Although not shown, the gate electrode 14, the gate line 12 and the gate pad 16 are formed of a low resistance metal layer, such as aluminum (Al) and Al alloy, and a barrier metal layer, such as molybdenum (Mo) and chromium (Cr) underneath the low resistance metal layer. Similarly, although not shown, the source electrode 24, drain electrode 26, the data line 28 and the data pad 30 include the same low resistance metal layer as the gate electrode 14, the gate line 12 and the gate pad 16, and lower and upper barrier metal layers. At this time, the low resistance metal layer for the source electrode 24, drain electrode 26, the data line 28 and the data pad 30 is interposed between the lower and upper barrier metal layers.
FIGS. 2A to 2E, 3A to 3E and 4A to 4E are schematic cross-sectional views taken along lines II-II, III-III and IV-IV in FIG. 1 that show the fabricating process of an array substrate for a liquid crystal display device. FIGS. 2A to 2E show one pixel region that includes a thin film transistor. FIGS. 3A to 3E show an area of a gate pad, and FIGS. 4A to 4E show any area of a data pad.
As shown in FIGS. 2A, 3A and 4A, a gate line 12, a gate electrode 14 and a gate pad 16 are formed on a substrate 10 as a double metal layer such that a first metal layer 11a is formed of Al or Al alloy and a second metal layer 11b is formed of chromium (Cr), titanium (Ti), molybdenum (Mo), tantalum (Ta) and Mo-tungsten (W) alloy. For convenience, the gate line 12, the gate electrode 14 and the gate pad 16 will subsequently be collectively referred to as a gate pattern 11.
In FIGS. 2B, 3B and 4B, a gate insulating layer 18 of an insulating material, such as silicon nitride (SiNx), is formed over the entire surface of the gate pattern 11. Sequentially, an active layer 20 of intrinsic amorphous silicon and an ohmic contact layer 22 of impurity-doped amorphous silicon are formed on the gate insulating layer 18.
Next, as shown in FIGS. 2C, 3C and 4C, a source electrode 24, a drain electrode 26, a data line 28 and a data pad 30 are formed as a triple metal layer over the substrate 10 having the active layer 20 and the ohmic contact layer 22. For convenience, the source electrode 24, the drain electrode 26, the data line 28 and the data pad 30 will subsequently be collectively referred to as a data pattern 23.
As shown in regions EV1 and EV2 of FIGS. 2C and 4C, the drain electrode 26 and the data pad 30 include a third metal layer 23a of the same material as the first metal layer 11a in FIGS. 2A, 3A and 4A, a fourth metal layer 23b of the same material as the second metal layer 11b in FIGS. 2A, 3A and 4A, and a fifth metal layer 23c of the same material as the third metal layer 23a. Although not shown, the source electrode 24 and the data line 28 have the same laminated structure as the drain electrode 26 and the data pad 30.
The third metal layer 23a functions as a barrier layer for the fourth metal layer 23b to reduce contact resistance of the fourth metal layer 23b with the ohmic contact layer 22. The fifth metal layer 23c functions as another barrier layer for the fourth metal layer 23b to reduce contact resistance of the fourth metal layer 23b with a transparent conductive metal layer that will be formed in a subsequent process. When the fourth metal layer 23b is formed of intrinsic Al, the third metal layer 23a prevents a spiking phenomenon of the fourth metal layer 23b. The spiking phenomenon is a contact defect between an Al layer and a silicon layer, such as the fourth metal layer 23b and the ohmic contact layer 22. The third metal layer 23a also prevents the formation of Al oxide (Al2O3) caused by oxidation on the surface of the fourth layer 23b. When the fourth metal layer 23b is selected from Al or Al alloy, for example, and the third and fifth metal layers 23a and 23c is selected from Cr or Mo, for example.
Next, as shown in FIGS. 2D, 3D and 4D, a passivation layer 32 is formed of inorganic materials, such as SiNx and SiOx, or organic materials, such as benzocyclobutene (BCB) and acrylic resin. A first contact hole C1 in the passivation layer 32 exposes a portion of the drain electrode 26. A second contact hole C2 in the passivation layer 32 exposes a portion of the gate pad 16. A third contact hole C3 in the passivation layer 32 exposes a portion of the data pad 30. The second contact hole C2 is also formed in the gate insulating layer 18 as well as the passivation layer 32. In other words, the gate insulating layer 18 and the passivation layer 32 both commonly have the second contact hole C2, as shown in FIG. 3D.
Next, as shown in FIGS. 2E, 3E and 4E, a pixel electrode 34, a gate pad terminal 36 and a data pad terminal 38 are formed by depositing and patterning transparent conductive materials, such as indium tin zinc oxide (ITZO) on the entire surface of the passivation layer 32. At this time, the pixel electrode 34 connects to the drain electrode 26 via the first contact hole C1, and the gate pad terminal 36 and the data pad terminal 38 are connected to the gate and data pads 16 and 30 via the second and third contact holes C2 and C3, respectively. For convenience, the pixel electrode 34, the gate pad terminal 36 and the data pad terminal 38 will subsequently be collectively referred to as a pixel pattern 33. The fifth metal layer 23c of the data pattern 23 in FIGS. 2C, 3C and 4C functions as the barrier layer for the fourth metal layer 23b of the data pattern 23 in FIGS. 2C, 3C and 4C and the pixel pattern 33.
When the electrodes and the lines are formed of low resistance metallic materials, signal speed improves. A barrier layer can prevent a reduction in resistance value caused by being oxidization of the low resistance metallic material. In addition, a barrier layer prevents contact defects during the process of patterning the low resistance metal layer. Moreover, when the low resistance metallic material is used in the data pattern, such as the source electrode, the drain electrode, the data line and the data pad, the data pattern should further include upper and lower barrier layers as well as the low resistance metal layer. Therefore, the process time and cost increase for fabricating an LCD device according to the related art.